The invention pertains to a high-speed sense amplifier. Particularly, the invention pertains to such a sense amplifier adapted for use with a directory memory array "chip".
Referring to FIG. 1 of the drawings, a block diagram of a typical directory chip is shown. Data inputted first to either of two registers 11 and 12 (registers A and B) is directed by a write logic circuit to a selected one of arrays 0 to 3, which together make up a memory block 17. Steering of the data from the write logic circuit 14 to the various arrays of the memory block 17 is done under control of the write select circuit 13. As indicated in the drawings, each of the registers 11 and 12 may be nine bits wide, although any desired practical number can be utilized. Accordingly, each of the arrays 0 to 3 is also nine bits wide. The arrays 0 to 3 each store 32 nine-bit bytes of data. The array location where a particular byte of data is to be stored or read out is indicated by a word decoder 16.
The nine-bit outputs from the arrays 0 to 3 are fed to an input port of a byte select circuit 22. The byte select circuit 22 functions both as a sense amplifier circuit for each of the arrays 0 to 3 and as a data driver circuit for driving the sensed signals and applying them to a compare logic circuit 21 and a set of data drivers 24. More specifically, it is the function of the byte select circuit 22 to sense the output of memory cells designated by the output of the word decoder 16, transmit data to the compare logic 21 directly representing the corresponding sensed bit states or levels (the terms "state" and "level" are used interchangeably throughout the present application), and to transmit to the data drivers 24, on a bus 25, data bits DB.sub.0 to DB.sub.8 which correspond to the output of only one of the arrays 0 to 3, particularly, one of the arrays 0 to 3 specified by the output of a read decode circuit 18.
The compare logic circuit 21 compares the nine-bit bytes from each of arrays 0 to 3 as sensed and transmitted by the byte select circuit 22 with a single nine-bit (CD.sub.0 to CD.sub.8) byte of comparison input data provided through a compare input circuit 19 on a bus 29. A single bit indicative of the result of each nine-bit comparison is generated by the compare logic circuit 21 and applied to compare drivers 27 which provide corresponding drive signals on a bus 8. The data drivers 24 select as an output onto an output bus 15 either the output of the byte select circuit 22 or the comparison input data on the bus 29 from the output of the compare input circuit 19. The selection is made in accordance with the output of a bypass select circuit 23, which in turn makes the selection based upon the state of a bypass signal BPS.
It is with the byte select circuit 22 that the invention is most closely related. Referring now to the block diagram of FIG. 2, an alternative approach (as disclosed in U.S. Pat. No. 4,460,984 and assigned in common with the present application) for constructing the byte select circuit 22 is depicted. Circuitry for one of 36 bit positions is shown; the circuitry for the other bit positions would be essentially identical.
The output from each bit position of each of the arrays is in the form of two bit lines per memory cell. More specifically, when a memory cell 31-0 to 31-n is being sensed, one of bit lines B0.sub.n and B1.sub.n will carry a current in the direction of a sense amplifier 32. That is, one, but not both, of the lines B0.sub.n and B1.sub.n will carry current to indicate whether the corresponding memory cell stores a logical 0 or logical 1, respectively. The output of the sense amplifier 32, specifically, compare bits C0.sub.n and C1.sub.n, are applied to an exclusive-OR circuit 33, which is one of 36 such circuits in the compare logic 21. The exclusive-OR circuit 33 compares the data bit indicated by the relative states of C0.sub.n and C1.sub.n with a corresponding comparison input bit from the bus 29. The output of the sense amplifier 32 is also coupled to an input port of an inhibit logic circuit 34. Depending on the state or level of an INHIBIT signal applied to the inhibit logic circuit 34, a single-bit signal D.sub.n, which has a voltage level determined by which of C0.sub.n and C1.sub.n is active, is selectively applied to the input of a driver circuit 36. That is, if the INHIBIT signal is in the 0 state, the inhibit logic circuit 34 inhibits the communication of its output bit D.sub.n to the input of the driver 36, while if the INHIBIT signal is in the logical 1 state, the inhibit logic circuit 34 is made to transmit the bit D.sub.n to the input of the driver circuit 36. Outputs of inhibit logic circuits 34 for like-ordered bits of each of the four bytes are wired-OR at the input of the driver 36. Of course, only one of the inhibit logic circuits 34 out of the four like-ordered inhibit logic circuits can be permitted to transmit its output bit to the driver 36 at any one time. The driver 36 produces, for each output bit DB.sub.n two signals, DB0.sub.n and DB1.sub.n, one of which is activated (in the UP state) to indicate the state of the bit DB.sub.n.
Referring now to the schematic diagram of FIG. 3, the construction of the portion of the byte select circuit 22 shown in FIG. 2 will be explained in detail. The sense amplifier 32 is composed of a differential amplifier formed by transistors 51 and 52, the outputs of which are amplified and buffered by corresponding emitter-follower connected transistors 54 and 56. A transistor 53 provides a reference voltage to the bases of the transistors 51 and 52. The output lines B0.sub.n and B1.sub.n from the corresponding bit of the respective memory array are applied to the emitters of the transistors 51 and 52, respectively. The signals C0.sub.n and C1.sub.n are generated at the emitter outputs of the transistors 54 and 56, respectively. These are applied, as shown in FIG. 2, directly to the exclusive-OR circuit 33. Also, C0.sub.n and C1.sub.n are applied to bases of respective transistors 57 and 58, which are connected in a differential amplifier configuration within the inhibit logic circuit 34. A constant current is supplied to the commonly connected emitters of the transistors 57 and 58 from a current source transistor 60 through a current switch transistor 59. A reference for the transistor 60 is supplied through transistors 62 and 63.
An emitter-follower coupled transistor 61 receives at its base the output from the collector of the transistor 58. The signal D.sub.n is thereby produced at the emitter of the transistor 61. A current switch transistor 55 is connected between the collector of the transistor 58 and base of the transistor 61, on one hand, and the collector of the current source transistor 60 on the other. The INHIBIT signal is applied to the base of the transistor 55. If the INHIBIT signal is in the DOWN logic state, that is, if INHIBIT is more negative than V.sub.REF, the transistor 55 is turned off, permitting the current generated through the transistor 60 to flow through the transistor 59, hence activating the differential amplifier circuit formed by the transistors 57 and 58. On the other hand, if INHIBIT is more positive than V.sub.REF, the transistor 55 is turned on, thereby "stealing" the current from the transistor 59. This has the effect of shutting off the transistor 61. Hence, the signal D.sub.n is passed to the driver circuit 36 only in the case that the INHIBIT signal is in the DOWN logic state.
The driver circuit 36 is composed of a differential amplifier formed by transistors 64 and 66. The D.sub.n signal from the emitter of the transistor 61 of the inhibit logic circuit 34 is applied to the base of the transistor 66. A reference voltage, generated by a circuit composed of transistors 67, 68, 69 and 71 and associated resistors, is applied to the base of the transistor 61. D1.sub.n and D0.sub.n are generated at the emitters of the transistors 64 and 66, respectively.
Although the circuit of FIG. 2 can perform the desired basic functions of the byte select circuit 22 of FIG. 2, nevertheless, it suffers from a number of serious drawbacks. First of all, as can be readily seen from even a brief consideration of FIG. 3, the circuitry is quite complex, and it requires a considerable chip area. Secondly, the power required for operating this circuit is considerable. Thirdly, a differential delay is encountered between C0.sub.n, C1.sub.n and D0.sub.n, D1.sub.n due to the presence of the inhibit logic circuit 34.
Accordingly, it is an object of the present invention to provide a high-speed sense amplifier which performs the necessary functions of a byte select circuit in a directory chip, but in which the above-mentioned drawbacks have been eliminated.